1. Field of Invention
This invention relates in general to satellite navigation systems and in particular to Global Positioning System (“GPS”) receivers utilizing Radio Frequency (“RF”) receivers integrated onto a single integrated circuit (“IC”).
2. Related Art
The use of telecommunication devices in present day society has grown at an enormous rate. At present, the demand for portable telecommunication devices such as cellular telephones, Wi-Fi® and Bluetooth® enabled portable devices, Personal Communication Service (“PCS”) devices, Global Positioning System (“GPS”) enabled portable devices, etc., is growing in popularity every day. As the demand increases for portable telecommunication devices with varying communication characteristics, manufacturers are seeing a need to combine and integrate many of these devices. As an example, there is a need to integrate cellular telephones (i.e., “cellphones”) with GPS receivers in order to allow a cellphone to determine its position for both personal and emergency use.
As the need to combine multiple telecommunications devices grows and also as the need to integrate them into a minimum number of integrated circuits (“ICs” also known as “chips”) increases, there is a need to eliminate any unnecessary circuitry to reduce the area size of the circuitry and the associated costs. A known technique for reducing costs and area size in telecommunication device receivers is to integrate the receivers on to a single IC creating what is commonly known as a Radio Frequency Integrated Circuit (“RFIC”) receiver.
Unfortunately, most existing RFIC receivers are not capable of being fully integrated because they use external RF filters that utilize Surface Acoustic Wave (“SAW”), Bulk Acoustic Wave (“BAW”), or ceramic technology. The reason for this is that these external RF filters are typically discrete components and the Q-factor that can be achieved in SAW, BAW, and ceramic technology is higher than can be achieved in silicon leading to better performance within the RFIC receiver circuitry.
As an example, in FIG. 1 a block diagram of an example of a known implementation of an RFIC receiver 100 is shown. In this example, the RFIC receiver 100 may be in signal communication with an external RF filter 102 and may include a low-noise amplifier (“LNA”) 104, optional RF amplifier 106, mixer 108, a frequency reference 109, and a phase-locked loop (“PLL”) 110. As an example, the RF filter 102 may be in signal communication with both the LNA 104 and optional RF amplifier 106 via signal paths 112 and 114, respectively. The mixer 108 may be in signal communication with both optional RF amplifier 106 and PLL 110 via signal paths 116 and 118, respectively.
The PLL 110 may include a phase detector 120, loop filter 122, divide-by-N divider 124, and a voltage-controlled oscillator (“VCO”) 126. The phase detector 120 may be in signal communication with both loop filter 122, divide-by-N divider 124, and frequency reference 109 via signal paths 128, 130, and 131, respectively. The VCO 126 may also be in signal communication with the mixer 108, the loop filter 122 and divide-by-N divider 124 via signal paths 118, 132 and 134, respectively, where signal paths 118 and 134 may be the same signal path. It is appreciated by those skilled in the art that in general, a PLL (such as PLL 110) is a circuit architecture that acts as a closed-loop frequency control system, which functions based on phase-sensitive detection of any phase difference between a reference input 135 and the divided output 136 of the controlled oscillator (such as VCO 126).
In an example of operation, the RFIC receiver 100 receives an input RF signal 137 at the LNA 104. The LNA 104 amplifies the input RF signal 137 to create an amplified signal 138 and passes the amplified signal 138 to the external RF filter 102. The external RF filter 102 filters the amplified signal 138 to create a filtered signal 140 and passes the filtered signal 140 to the optional RF amplifier 106. The optional RF amplifier 106 amplifies the filtered signal 140 to create a second amplified signal 142 and passes the second amplified signal 142 to the mixer 108. The mixer 108 then mixes the second amplified signal 142 with a local oscillator (“LO”) signal 144 (which was produced by the PLL 110) and produces a resultant signal 146. Within this process, the PLL 110 utilizes a frequency reference signal 135 to “lock” the VCO 126 to a multiple frequency of the frequency reference signal 135.
Generally, in multiple RF transceiver applications (such as cellphone applications) with large interferers, the GPS receiver may require that two SAW filters are used; one before the LNA (generally known as a pre-filter) and one between the LNA and the mixer. As cellphones and other portable telecommunication devices become smaller and less costly, there is increasing pressure to eliminate one or more of these SAW filters to save area and cost. Typically, other receivers often have similar problems and similar solutions.
Additionally, while an integrated (i.e., “on-chip”) RF filter may not perform as well as an external SAW filter, they now have the potential of performing well enough to eliminate one SAW filter in applications that currently require two SAW filters because of the improvement of performance of on-chip spiral inductors, thus reducing the total system implementation size and cost.
However, due to Process-Voltage-Temperature (“PVT”) variations, on-chip RF filters must be tuned or calibrated to maintain their frequency response. Unfortunately, tuning circuits consume power and area on-chip, and they also increase the complexity and risk of failure of the on-chip RF filter.
Therefore, there is a need for a system and method capable of auto-tuning and/or auto-calibrating an on-chip RF filter without requiring any additional tuning circuitry, other than what is already present in the PLL synthesizer of the RF receiver.